Temperature and voltage compensated multivibrator



Aug. 2, 1966 R. MARCUS 3,264,579

TEMPERATURE AND VOLTAGE COMPENSATED MULTIVIBRATOR Filed Feb. 15, 1964 5 Sheets-Sheet 1 Pmmz g;

a j M/VE/VTOE, F/ [/84 fi. MA /e605 I. R. MARCUS Aug. 2, 1966 TEMPERATURE AND VOLTAGE COMPENSATED MULTIVIBRATOR Filed Feb. 13, 1964 5 Sheets-Sheet 2 //Vl EN7'0A, [m 6 M/wcus 7M ,q M 5,9. 0 Edy/IA,

ATTORNEYS United States Patent 3,264,579 TEMPERATURE AND VOLTAGE CGMPENSATED MULTWIBRATOR Ira R. Marcus, Wheaten, Md, assignor to the United States of America as represented by the Secretary of the Army Filed Feb. 13, 1964, Ser. No. 344,787 4 Claims. (Cl. 331-413) The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment to me of any royalty thereon.

This invention relates generally to multivibrator circuits, and more particularly to astable multivibrator circuits having highly stable output frequencies for large variations of ambient temperature and power supply voltage.

In digital electronic timing and programming devices the accuracy of the system depends upon the accuracy of the time base. Often the time base is established by an astable multivibrator. Many digital devices, such as for example field test equipment, timers and control mechanisms, are subjected to large changes in ambient temperature and are not provided with well regulated power supplies. Both changes in temperature and variations in supply voltage affect the frequency of an astable multivibrator.

It is therefore an object of the present invention to provide a temperature compensated multivibrator circuit.

It is another object of the invention to provide an astable multivibrator circuit having an output frequency which is substantially invariant with changes in supply voltage.

It is a further object of the instant invention to provide an astable multivibrator which is both temperature and voltage compensated and provides an output which is a true square wave.

According to the present invention, the foregoing and other objects are attained by providing within an astable multivibrator circuit comprising two transistors, means for supplying voltage to the base circuits of the two transistors which voltage varies in a manner that compensates for the variation in the base to emitter voltages of the transistors due to changes in ambient temperature and supply voltage and means for supplying voltage to the collector circuits of the two transistors which voltage varies in a manner that compensates for the variation in the saturation collector to emitter voltages of the transistors due to changes in ambient temperature and supply voltage.

The specific nature of the invention, as well as other objects, aspects, uses and advantages thereof, will clearly appear from the following description and from the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a typical prior art astable multivibrator circuit;

FIG. 2 is a schematic diagram of a first order temperature and voltage compensated astable multivibrator circuit according to the invention;

FIGv 3 is a schematic diagram of another first order temperature and voltage compensated astable multivibrator cincuit according to the invention;

FIG. 4 is a schematic diagram of a second order temperature and voltage compensated astable multivibrator circuit according to the invention;

FIG. 5 is a schematic diagram of a second order temperature and voltage compensated astable multivibrator which provides a true square wave output;

FIGS. 6A, 6B, 6C and 6D are graphical representations of the waveforms of the astable multivibrator shown in FIGURE 1; and

"ice

FIGS. 7A, 7B, 7C and 7D are graphical representations of the astable multivibrator shown in FIGURE 5.

Referring now to the drawings wherein like reference numerals designate identical or corresponding parts throughout the several figures, and more particularly to FIGURE 1 wherein there is shown a typical prior art astable multivibrator circuit. This circuit is shown as comprising two NPN transistors 2 and 3 which are powered by a source of positive potential (not shown) connected to terminal 1. Cross-coupling capacitors 6 and 7 interconnect the collectors of transistors 2 and 3, respectively, with the bases of transistors 3 and 2, respectively. Resistors 4 and 5 connect the collectors of transistors 2 and 3, respectively, to terminal 1 while resistors 8 and 9 connect the bases of transistors 2 and 3, respectively, to terminal 1. Briefly, the operation of this circuit is as follows: Assume that transistor 3 has just turned off. The collector to emitter voltage V of transistor 3 then rises from the collector to emitter saturation voltage V of transistor 3 to the supply voltage V which is supplied to the circuit at terminal 1 through the charging path comprising resistor 5 and capacitor 7. This is shown in FIGURE 60, which shows the voltage waveform at the collector of transistor 3. The base to emitter voltage V of transistor 3 also rises from a voltage equal to (V-V V where V is the collector to emitter saturation voltage of transistor 2 and V is the minimum base to emitter voltage that causes transistor 3 to turn on, toward the supply voltage V through the charging path comprising resistor 8 and capacitor 6. When V reaches voltage V transistor 3 turns on, and V drops to V This is shown in FIGURES 60, which shows the voltage waveform at the collector of transistor 3, and 6D, which shows the voltage waveform at the base of transistor 3. The base to emitter voltage V of transistor 2 then drops to a voltage equal to (V V V Where V is the minimum base to emitter voltage that causes transistor 2 to turn on, causing transistor 2 to turn off. When transistor 2 turns off, its collector to emitter voltage V rises from V to V through the charging path comprising resistor 4 and capacitor 6. This is shown in FIGURE 6A, which shows the voltage waveform at the collector of transistor 2. The base to emitter voltage V of transistor 2 also rises from through the charging path comprising resistor 9 and capacitor 7 toward supply voltage V. When V reaches V transistor 2 turns on causing transistor 3 to turn ofi since V drops to (VV V This is shown in FIGURES 6A, which shows the voltage waveform at the collector of transistor 2, and 6B, which shows the voltage waveform at the base of transistor 2. The cycle then repeats. Good design requires resistors 4 and 5 to have a low enough resistance to assure that transistors 2 and 3 saturate when they are on and the time constants R C and R C; to be less than the time constants R 0, and Rgcs, respectively, so that the collector voltages will go to the supply voltage during the times that transistors 2 and 3, respectively, are off.

The period of oscillation of the circuit shown in FIG- URE 1 is expressed as follows:

where P is the periodin seconds,T is the time in seconds that transistor 3 is off, T is the time in seconds that tran-;

sistor2 is off, R and R are the resistances of resistors 8 and 9, respectively, in ohms, and C and C are the capacitances of capacitors 6 and 7, respectively, in farads.

constant :for changes in ambient temperature and supply voltage, the condition that thefrequency of the circuit of FIGURE; 1 is invariant with temperature-and voltage requires that the ratios V V V-V and remain constant. and the minimum base to emitter voltages V and V1 are, however, dependent on both the supply voltage and the ambient temperature. Compensation for those voltages is therefore required.

FIGURE 2 shows an astable multivibrator circuit which uses a diode to compensate for the minimum base to emitter voltages V and V This circuit is substan tially the same as that shown in FIGURE 1 exceptthat Assuming that the timeconstants R C and' R C are- The saturation voltages V and V H the voltage supplied to the collectors of the transistors i 2 and 3 by way of resistors 4-and 5 isqderived from a voltage divider comprising diode 10 and resistor 11.

Also, the transistors 2 and 3 are the PNPtype requiring I the voltage supplied at terminal 1 to benegative. If it is assumed that the transistors 2 and 3 are matched, i.e,

oscillation of this circuit is expressed as follows:

where V is the voltage drop across the diode 10. V

is adjusted to be equal to V by adjusting the value of the resistance of resistor 11. V is neglected since it is an orderof magnitude smaller tharrV Now if diode 10 is chosen so as to have the same temperature coefiicient" for-V as that for V ,the ratio VV V-V ,is substantially constant forchanges in ambient temperature- The ratio varies slightly with changes in supply voltage since V is afiected more by changes in supply voltage 1 than is VB since the current through diode It! varies with supply voltage.

FIGURE 3 shows anrastable multivibrator circuit:

which uses a transistor to compensate for the minimum base to emitter voltages V and V This circuit is substantially the same as the circuit shown inFIGURE 2 except that NPN transistor 12 replaces diode 10. Volt- 1 age is supplied to the collectors of transistors 2 and 3 by way of resistors 4 and 5 from the base of-transistor 12. Again assuming that transistors 2 and 3 are matched,

the period of oscillation'of'this circuit is expressed as follows:

where V is the base to emitter; voltage of transistor 12; VBE12 is adjusted to equal V by adjusting the value of resistance of resistor 11. Temperature and voltage.

compensation of this circuit is about the same as that of the circuit shown in FIGURE 2. This circuit, however,

requires less power since the resistance of resistor 11 using transistor-12 instead of diode 10 is an order of magnitude larger.

FIGURE 4 shows the first attempt at second order compensation. The circuit is substantially the same as the circuit shown in FIGURE 3 except that transistors 2 and 3 are the NPN type and transistor 12 is the PNP type requiring a positive voltage to be supplied at terminal 1. The circuit additionally includes PNP transistors '13 and 14 having base biasresistors 1'5. and 16; respectively. Transistors 13 and 1-4 have their emitters connected to terminal 1 and their collectors connected to resistors 8 and 9, respectively. These transistors are added to com- Pensaie the saturation VQltages Oftransistors :2 and P=RsCa ln [1+ and I 132 133 312 then the ratios VBE2'. 52 133 513 and VBE12, s3 ia2 514 are constant and the frequency is stable with changes in ambient temperatureand power supply-voltage. V and V however, depend on operating points determined by base and collector resistors; therefore, the-conditionassumed above requires that all the resistors in the circuit be equal. This is because resistors 8 and 9 "are the base resistors of transistors: 2 Land 3, respectively,v and .at the same, time are the collector resistors of transistors 13 and 14; respectively; Similarly,; resistors -4 and. 5 are. thebase resistors of'transistor 12iand the collector resistors ,of transistors 2,.andn3, respectively: With'all the resistances equal, the circuit no longer oscillates, since.

reliable operation requires that the time constants R 0 and R 0, be much ;le'ss=than the time constants R C t and R 'C respectively.

FIGURE. 5 shows the circuit of FIGURE 14 modified so as to allow oscillation-with the resistances of resistors 4, 5, 8 and 9 equal.

In FIGURE 5, it will be understooduthat theelements identified by numerals between 1 and 16' iinclu'sive correspond to the elements lof FIGUREEA- having like nu- Thus the purpose for which transistor 12in merals. FIGURE .5 is utilized corresponds to the purpose "for which transistor 12 in FIGURE 4, and also transistor 12in FIGURE 3, isutilized; transistor 12,.'in:combina-,

tion with resistor ILi'PIOdIlCES a controlled voltage at the base of transistor 12 that compensates, in a manner that would not occur: if resistors 4 and 5 ;Were connected directly to source .1, for changes in temperature andfor changes in the voltage supplied to source In FIGURE. 5 transistor-s19, and 20; havebase resistors 21 and 22, !respe ctively, which are also collector resistors of transistors -2Zand '3, respectively. Transistor 17 and.

resistor lsrform a voltage divider :for :supplying voltage to the emitters of transistors 19. and 20.! Transistor 19 is biasedzto conductwhen transistor=2 is on; Underthis condition, capacitor 7 is. charged through resistor :23,

transistor 11-9, and transistor '17 "from the voltage source connected to terminalhl. Resistor 23 .is smaller: thanre-z sistor 5;i the refore, the time constant R 30; is'small com- .pared-c with thetime constant R 05.

sistor 20 is biased to conductwhen transistor 3 is on..

Capacitor 6 is then charged through :resistor 24-,ktransistor 20, andtransistor17 fromithe voltage sourcecon-r nected to terminal :1. Resistor 24 isismaller than resistor 4; therefore the time constant R C is; small compared.

with the time constant 'RL C Compensation is not required for the collector to emitter saturation voltages V5 and V oftransistors 19 and20 because. they vanish when the chargingcurrents through themygo to zero. .Diodeslszandr 26 are used to isolate R, from C and- R fI'OIl'LCq, respectively. Diodes 27 and 28 are added to compensate for the voltages V1325 and V1326 across diodes 25 .and 26,respectively'.- Briefly, the operation of thiscircuit is asv followsz Assume that-transistor 3 has just turned vofl. The'collector 'to emitter voltage V Similarly, tran-= of transistor 3 then rises substantially instantaneously from the collector to emitter saturation voltage V of transistor 3 to the voltage equal to V- V where V is the supply voltage at terminal 1 and V is the base to emitter voltage of transistor '12. This is shown in FIGURE 7C, which shows the voltage waveform at the collector of transistor 3. The base to emitter voltage V of transistor 3 also rises from a voltage equal to (V-VBE17VD25VS2VB3), where V is the base of emitter voltage of transistor :17, V1325 is the voltage across diode 25, V is the collector to emitter saturation voltage of transistor 2, and V is the minimum base to emitter voltage that causes transistor 3 to turn on, toward a voltage equal to V-V V where V is the collector to emitter saturation voltage of transistor 13 and V1327 is the voltage across diode 27, through the charging path comprising resistor 8 and capacitor 6. When V reaches voltage V transistor 3 turns on, and V drops to V This is shown in FIGURES 7C, which shows the voltage waveform at the collector of transistor 3, and 7L1), which shows the voltage waveform at the base of transistor 3. The base to emitter voltage V of transistor 2 then drops to a voltage q to BE17 D26 s3 B2): when? VD26 is the voltage across diode 26 and V is the minimum base to emitter voltage that causes transistor 2 to turn on, causing transistor 2 to turn off. When transistor 2 turns off, its collector to emitter voltage V rises substantially instantaneously from V to VV This is shown in FIGURE 7A, which shows the voltage waveform at the collector of transistor 2. The base to emitter voltage V of transistor 2 also rises from through the charging path comprising resistor 9 and capacitor 7 toward a voltage equal to VV V where V is the collector to emitter saturation voltage of transistor '14 and V1328 is the voltage across diode 28. When V reaches V transistor 2 turns on causing transistor 3 to turn off since V3133 drops to This is shown in FIGURES 7A, which shows the voltage waveform at the collector of transistor 2, and 7B, which shows the voltage waveform at the base of transistor 2. The cycle then repeats. It is to be noted that the waveforms at the collectors of transistors 2 and 3 are true square waves.

The period of oscillation of the circuit shown in FIG- URE 5 is expressed as follows:

For voltage and temperature compensation the following parameters are matched: V and V V and V ern-1, 132 and isa; VD26 and 1328; and 025 and 1227- The resistors 8 and 9 and the capacitors 6 and 7 are temperature compensated.

It will be apparent that the embodiments shown are only exemplary and that various modifications can be made in construction and arrangement within the scope of the invention as defined in the appended claims.

I claim as my invention:

1. In an astable multivibrator having a first transistor and a second transistor each of said first and second transistors having a base electrode, an emitter electrode, and a collector electrode, said emitter electrodes being connected to circuit ground, a first capacitor connected to the collector electrode of said first transistor and to the base electrode of said second transistor, a second capacitor connected to the collector electrode of said second transistor and to the base electrode of said first transistor, a source of voltage, -a first resistor having first and second terminals, said first terminal connected to the collector electrode of said first transistor, a second resistor having first and second terminals, said first terminal of said second resistor connected to the collector electrode of said second transistor, a third resistor having first and second terminals, said first terminal of said third resistor connected to the base electrode of said first transistor and said second terminal of said third resistor connected to said source of voltage, a fourth resistor having first and second terminals, said first terminal of said fourth resistor connected to the base electrode of said second transistor and said sec-ond terminal of said fourth resistor connected to said source of voltage, an improved voltage-controlling device for supplying a controlled voltage to said first and second resistors, said device comprising:

(a) a third transistor having its emitter connected to said source of voltage and its base connected to said second terminal of said first resistor and said second terminal of said second resistor; and

(b) a fifth resistor connected between the collector of said third transistor and circuit ground, the value of said fifth resistor being such as to cause the baseto-emitter voltage of said third transistor to be equal to the minimum base-to-emitter voltage which causes said first and second transistors to conduct.

.2. The improvement recited in claim 1 further comprising a first semiconductor device interposed between and source of voltage and said third resistor and a second semiconductor device interposed between said source of voltage and said fourth resistor, the voltage drop across said first semiconductor device being equal to the collector to emitter saturation voltage of said second transistor and the voltage drop across said second semiconductor device being equal to the collector to emitter saturation voltage of said first transistor.

3. The improvement recited in claim 2 where said first semiconductor device is a *fourth transistor and said second semiconductor device is a fifth transistor, each of said fourth and said fifth transistors having a base electrode, an emitter electrode, and a collector electrode, and further comprising a sixth resistor and a seventh resistor, said sixth resistor being connected between said base electrode of said fourth transistor and ground for supplying a base bias voltage to said fourth transistor, said seventh resistor being connected between said base electrode of said fifth transistor and ground for supplying a base bias voltage to said fifth transistor, said source of voltage being connected to both said emitter electrodes of said fourth and fifth transistors, said third resistor being connected to said collector electrode of said fourth transistor, and said fourth resistor being connected to said collector electrode of said fifth transistor.

4. The improvement recited in claim 3 wherein said first, second, third, and fourth resistors have equal resistance values, said improvement further comprising first means connected between said first resistor and said first capacitor for isolating said first resistor from said first capacitor, second means connected between said second resistor and said second capacitor for isolating said second resistor from said second capacitor, third means connected between said source of voltage and said first capacitor for charging said first capacitor when said first transistor is not conducting, and fourth means connected between said source of voltage and said second capacitor for charging said second capacitor when said second transistor is not conducting.

References Cited by the Examiner UNITED STATES PATENTS 3,178,658 4/1965 Henrion 331--1l3 X ROY LAKE, Primary Examiner.

J. B. MULLINS, Assistant Examiner. 

1. IN AN ASTABLE MULTIVIBRATOR HAVING A FIRST TRANSISTOR AND A SECOND TRANSISTOR EACH OF SAID FIRST AND SECOND TRANSISTORS HAVING A BASE ELECTRODE, AN EMITTER ELECTRODE, AND A COLLECTOR ELECTRODE, SAID EMITTER ELECTRODES BEING CONNECTED TO CIRCUIT GROUND, A FIRST CAPACITOR CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR, A SECOND CAPACITOR CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR AND THE BASE ELECTRODE OF SAID FIRST TRANSISTOR, A SOURCE OF VOLTAGE, A FIRST RESISTOR HAVING FIRST AND SECOND TERMINALS, SAID FIRST TERMINAL CONNECTED TO THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR, A SECOND RESISTOR HAVING FIRST AND SECOND TERMINALS, SAID FIRST TERMINAL OF SAID SECOND RESISTOR CONNECTED TO THE COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR, A THIRD RESISTOR HAVING FIRST AND SECOND TERMINALS, SAID FIRST TERMINAL OF SAID THIRD RESISTOR CONNECTED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR AND SAID SECOND TERMINAL OF SAID THIRD RESISTOR CONNECTED TO SAID SOURCE OF VOLTAGE, A FOURTH RESISTOR HAVING FIRST AND SECOND TERMINALS, SAID FIRST TERMINAL OF SAID FOURTH RESISTOR CONNECTED TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR AND SAID SECOND TERMINAL OF SAID FOURTH RESISTOR CONNECTED TO SAID SOURCE OF VOLTAGE, AN IMPROVED VOLTAGE-CONTROLLING DEVICE FOR SUPPLYING A CONTROLLED VOLTAGE TO SAID FIRST AND SECOND RESISTORS, SAID DEVICE COMPRISING: (A) A THIRD TRANSISTOR HAVING ITS EMITTER CONNECTED TO SAID SOURCE OF VOLTAGE AND ITS BASE CONNECTED TO SAID SECOND TERMINAL OF SAID FIRST RESISTOR AND SAID SECOND TERMINAL OF SAID SECOND RESISTOR; AND (B) A FIFTH RESISTOR CONNECTED BETWEEN THE COLLECTOR OF SAID THIRD TRANSISTOR AND CIRCUIT GROUND, THE VALUE OF SAID FIFTH RESISTOR BEING SUCH AS TO CAUSE THE BASETO-EMITTER VOLTAGE OF SAID THIRD TRANSISTOR TO BE EQUAL TO THE MINIMUM BASE-TO-EMITTER VOLTAGE WHICH CAUSES SAID FIRST AND SECOND TRANSISTORS TO CONDUCT. 